A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications

A phase-locked loop (PLL) for CMOS UltraSPARC microprocessor applications uses a loop filter referenced to a quiet power supply and achieves measured clock period jitter of /spl plusmn/25 ps at 360 MHz. The fully integrated CMOS PLL uses a charge-pump phase/frequency detector, a single-capacitor loo...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2000-03, Vol.35 (3), p.450-454
Main Authors: Hee-Tae Ahn, Allstot, D.J.
Format: Article
Language:English
Subjects:
Charge pumps
Clocks
Filters
Frequency measurement
Jitter
Microprocessors
Phase locked loops
Phase measurement
Power measurement
Power supplies
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Summary:A phase-locked loop (PLL) for CMOS UltraSPARC microprocessor applications uses a loop filter referenced to a quiet power supply and achieves measured clock period jitter of /spl plusmn/25 ps at 360 MHz. The fully integrated CMOS PLL uses a charge-pump phase/frequency detector, a single-capacitor loop filter, and a feedforward error correction architecture. Loop characteristics are analyzed and verified by measurements. The measured sensitivity of clock period jitter to supply voltage is 2.6 ps/100 mv over an analog supply-voltage range of 1.6-2.1 V; the measured output operating frequency range is 8.5-660 MHz. Fabricated in an area of 310/spl times/280 /spl mu/m/sup 2/ in a 0.25-/spl mu/m CMOS process, the PLL dissipates 25 mW from a 1.9-V supply.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.826829