Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing

We demonstrated a highly reliable buried-gate saddle-fin cell-transistor (cell-TR) using silicon migration technique of hydrogen (H 2 ) annealing after a dry etch to form the saddle-fin in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced...

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Bibliographic Details
Main Authors: Seong-Wan Ryu, Kyungkyu Min, Jungho Shin, Heimi Kwon, Donghoon Nam, Taekyung Oh, Tae-Su Jang, Minsoo Yoo, Yongtaik Kim, Sungjoo Hong
Format: Conference Proceeding
Language:English
Subjects:
Fabrication
Hafnium
hydrogen anneal
interface trap VRT and Row-Hammering
Random access memory
saddle finfet
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Summary:We demonstrated a highly reliable buried-gate saddle-fin cell-transistor (cell-TR) using silicon migration technique of hydrogen (H 2 ) annealing after a dry etch to form the saddle-fin in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced variable-retention-time (VRT) and Row-Hammering immunity.
ISSN:2156-017X
DOI:10.1109/IEDM.2017.8268437