DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG

Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2019-01, Vol.38 (1), p.136-148
Main Authors: Hsieh, Shih-An, Wang, Ying-Hsu, Shen, Ting-Yu, Huang, Kuan-Yen, Pai, Chia-Cheng, Chen, Tsai-Chieh, Li, James Chien-Mo
Format: Article
Language:English
Subjects:
Asynchronous circuits
Chain scission
Circuit design
Circuit faults
Circuits
Coloring
design for testability (DfT)
Direct reduction
Encoding
Feedback loops
Inverters
Latches
Logic gates
Pattern generation
Product testing
Registers
test pattern generation
Test pattern generators
Test systems
Testability
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Summary:Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2018.2801226