Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion

This work addresses the problem of automatically synthesizing compact standard cell layouts with 2D metal-1 routing under design rule constraints. Precisely, we propose a set of new highly impacting techniques dedicated solely to the generation of cell layouts with 2D metal-1 routing completion. Tho...

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Bibliographic Details
Main Authors: Jo, Kyeongrok, Ahn, Seyong, Kim, Taewhan, Choi, Kyumyung
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Layout
Logic gates
Microprocessors
Routing
Transistors
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Summary:This work addresses the problem of automatically synthesizing compact standard cell layouts with 2D metal-1 routing under design rule constraints. Precisely, we propose a set of new highly impacting techniques dedicated solely to the generation of cell layouts with 2D metal-1 routing completion. Those are (1) netlist decomposition (2) transistor chaining combined with transistor folding, (3) gate poly ordering combined with fast routing congestion estimation, and (4) 2D single-layer routing with minimal resource. It is shown from experiments that our proposed layout generator is able to produce layouts of quality comparable to the expert's manual ones, but spending just one hour for 56 representative cells generation.
ISSN:2153-697X
DOI:10.1109/ASPDAC.2018.8297373