System-on-chip security architecture and CAD framework for hardware patch

• Main Authors: Deb Nath, Atul Prasad, Ray, Sandip, Basak, Abhishek, Bhunia, Swarup
• Format: Conference Proceeding
• Language: English
• Subjects: Cryptography; Engines; Field programmable gate arrays; Hardware; IP networks; Registers
• ISSN: 2153-697X
• DOI: 10.1109/ASPDAC.2018.8297409

System-on-Chip (SoC) security architectures targeted towards diverse applications including Internet of Things (IoT) and automotive systems enforce two critical design requirements: in-field configurability and low overhead. To simultaneously address these constraints, in this paper, we present a novel, flexible, and adaptable SoC security architecture that efficiently implements diverse security policies. The architecture and associated CAD flow enable "hardware patching" i.e. hardware security policy engine that can be seamlessly and securely upgraded in field to address unanticipated attacks or new security requirements. We implement (1) a centralized Reconfigurable Security Policy Engine (RSPE), (2) smart security wrappers, and (3) Design-for-Debug (DfD) infrastructure interface as the building blocks of the architecture. The proposed framework provides a systematic approach to represent and synthesize diverse security policies. Through extensive analysis using representative SoC models, we show, for the first time to our knowledge, that the proposed framework provides high level of patchability with minimal energy and performance overhead.