Implementation of a tunable heterodyne notch filter

Simple hardware implementations of three key elements, (1) a fixed-coefficient prototype filter. (2) the digital up-converter, and (3) a digital down-converter are proposed for realization in FPGAs or ASICs. Through layout and simulation the feasibility of a tunable heterodyne notch filter is establ...

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Bibliographic Details
Main Authors: Azam, A., Sasidaran, D., Nelson, K.E., Ford, G.E., Seong-Jhin Choi, Johnson, L., Soderstrand, M.A.
Format: Conference Proceeding
Language:English
Subjects:
Computational modeling
Digital filters
Field programmable gate arrays
Finite impulse response filter
Hardware
IIR filters
Prototypes
Transfer functions
Tunable circuits and devices
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Summary:Simple hardware implementations of three key elements, (1) a fixed-coefficient prototype filter. (2) the digital up-converter, and (3) a digital down-converter are proposed for realization in FPGAs or ASICs. Through layout and simulation the feasibility of a tunable heterodyne notch filter is established in which three up-converters, four notch filters and three down-converters are combined to build a complete tunable heterodyne notch filter with more flexibility and less complexity than conventional tunable notch filters.
ISSN:1058-6393
2576-2303
DOI:10.1109/ACSSC.1999.832316