Design of a Gabor Filter HW Accelerator for Applications in Medical Imaging

The Gabor filter (GF) has been proved to show good spatial frequency and position selectivity, which makes it a very suitable solution for visual search, object recognition, and, in general, multimedia processing applications. GFs prove useful also in the processing of medical imaging to improve par...

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Bibliographic Details
Published in:IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2018-07, Vol.8 (7), p.1187-1194
Main Authors: Licciardo, Gian Domenico, Cappetta, Carmine, Di Benedetto, Luigi
Format: Article
Language:English
Subjects:
Accelerators
Biomedical imaging
CMOS
Comparative studies
Feature extraction
Field programmable gate arrays
field-programmable gate array (FPGA)
Filtration
Gabor filters
Gabor filters (GFs)
hardware (HW)
Image edge detection
Kernel
Medical imaging
Multimedia
Noise reduction
Object recognition
Power consumption
visual search (VS)
Visualization
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Summary:The Gabor filter (GF) has been proved to show good spatial frequency and position selectivity, which makes it a very suitable solution for visual search, object recognition, and, in general, multimedia processing applications. GFs prove useful also in the processing of medical imaging to improve part of the several filtering operations for their enhancement, denoising, and mitigation of artifact issues. However, the good performances of GFs are compensated by a hardware complexity that traduces in a large amount of mapped physical resources. This paper presents three different designs of a GF, showing different tradeoffs between accuracy, area, power, and timing. From the comparative study, it is possible to highlight the strength points of each one and choose the best design. The designs have been targeted to a Xilinx field-programmable gate array (FPGA) platform and synthesized to 90-nm CMOS standard cells. FPGA implementations achieve a maximum operating frequency among the different designs of 179 MHz, while 350 MHz is obtained from CMOS synthesis. Therefore, 86 and 168 full-HD (1920 × 1080) f/s could be processed, with FPGA and std_cell implementations, respectively. In order to meet space constraints, several considerations are proposed to achieve an optimization in terms of power consumption, while still ensuring real-time performances.
ISSN:2156-3950
2156-3985
DOI:10.1109/TCPMT.2018.2818947