Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs

Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the inter...

Full description

Saved in:
Bibliographic Details
Main Authors: Puschkarsky, Katja, Grasser, Tibor, Aichinger, Thomas, Gustin, Wolfgang, Reisinger, Hans
Format: Conference Proceeding
Language:English
Subjects:
BTI
CET
HTGS
Hysteresis
SiC
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔV th after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔV th after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.
ISSN:1938-1891
DOI:10.1109/IRPS.2018.8353560