Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs

Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the inter...

Full description

Saved in:
Bibliographic Details
Main Authors: Puschkarsky, Katja, Grasser, Tibor, Aichinger, Thomas, Gustin, Wolfgang, Reisinger, Hans
Format: Conference Proceeding
Language:English
Subjects:
BTI
CET
HTGS
Hysteresis
SiC
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c223t-1a2ce09e3f375c37ba5e976957da8c6c1a355b39d4e237fc39823430bc4623523
cites
container_end_page 3B.5-10
container_issue
container_start_page 3B.5-1
container_title
container_volume
creator Puschkarsky, Katja
Grasser, Tibor
Aichinger, Thomas
Gustin, Wolfgang
Reisinger, Hans
description Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔV th after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔV th after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.
doi_str_mv 10.1109/IRPS.2018.8353560
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_8353560</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8353560</ieee_id><sourcerecordid>8353560</sourcerecordid><originalsourceid>FETCH-LOGICAL-c223t-1a2ce09e3f375c37ba5e976957da8c6c1a355b39d4e237fc39823430bc4623523</originalsourceid><addsrcrecordid>eNotkMFKAzEYhKMgWGsfQLzkBXZN8m82yVGK2kKl4tpzySb_tpFtVjZB8O1dsafhm2HmMITccVZyzszD-v2tKQXjutQgQdbsgiyM0lyCrmWljL4kM25AF1wbfk1uUvpkTLApnZFmFz2OKdvoQzzQSehp8Nj_QR5tTAFjpvk4YjoOvaffQ5_tAWmIU6cNfcgB00S0CUv6um2enz7SLbnqbJ9wcdY52U32clVsti_r5eOmcEJALrgVDplB6EBJB6q1Eo2qjVTealc7bkHKFoyvUIDqHBgtoALWuqoWIAXMyf3_bkDE_dcYTnb82Z8_gF_sl1A3</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs</title><source>IEEE Xplore All Conference Series</source><creator>Puschkarsky, Katja ; Grasser, Tibor ; Aichinger, Thomas ; Gustin, Wolfgang ; Reisinger, Hans</creator><creatorcontrib>Puschkarsky, Katja ; Grasser, Tibor ; Aichinger, Thomas ; Gustin, Wolfgang ; Reisinger, Hans</creatorcontrib><description>Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔV th after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔV th after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.</description><identifier>EISSN: 1938-1891</identifier><identifier>EISBN: 9781538654798</identifier><identifier>EISBN: 1538654792</identifier><identifier>DOI: 10.1109/IRPS.2018.8353560</identifier><language>eng</language><publisher>IEEE</publisher><subject>BTI ; CET ; HTGS ; Hysteresis ; SiC</subject><ispartof>2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.3B.5-1-3B.5-10</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c223t-1a2ce09e3f375c37ba5e976957da8c6c1a355b39d4e237fc39823430bc4623523</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8353560$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8353560$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Puschkarsky, Katja</creatorcontrib><creatorcontrib>Grasser, Tibor</creatorcontrib><creatorcontrib>Aichinger, Thomas</creatorcontrib><creatorcontrib>Gustin, Wolfgang</creatorcontrib><creatorcontrib>Reisinger, Hans</creatorcontrib><title>Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs</title><title>2018 IEEE International Reliability Physics Symposium (IRPS)</title><addtitle>IRPS</addtitle><description>Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔV th after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔV th after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.</description><subject>BTI</subject><subject>CET</subject><subject>HTGS</subject><subject>Hysteresis</subject><subject>SiC</subject><issn>1938-1891</issn><isbn>9781538654798</isbn><isbn>1538654792</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2018</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkMFKAzEYhKMgWGsfQLzkBXZN8m82yVGK2kKl4tpzySb_tpFtVjZB8O1dsafhm2HmMITccVZyzszD-v2tKQXjutQgQdbsgiyM0lyCrmWljL4kM25AF1wbfk1uUvpkTLApnZFmFz2OKdvoQzzQSehp8Nj_QR5tTAFjpvk4YjoOvaffQ5_tAWmIU6cNfcgB00S0CUv6um2enz7SLbnqbJ9wcdY52U32clVsti_r5eOmcEJALrgVDplB6EBJB6q1Eo2qjVTealc7bkHKFoyvUIDqHBgtoALWuqoWIAXMyf3_bkDE_dcYTnb82Z8_gF_sl1A3</recordid><startdate>201803</startdate><enddate>201803</enddate><creator>Puschkarsky, Katja</creator><creator>Grasser, Tibor</creator><creator>Aichinger, Thomas</creator><creator>Gustin, Wolfgang</creator><creator>Reisinger, Hans</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201803</creationdate><title>Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs</title><author>Puschkarsky, Katja ; Grasser, Tibor ; Aichinger, Thomas ; Gustin, Wolfgang ; Reisinger, Hans</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c223t-1a2ce09e3f375c37ba5e976957da8c6c1a355b39d4e237fc39823430bc4623523</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2018</creationdate><topic>BTI</topic><topic>CET</topic><topic>HTGS</topic><topic>Hysteresis</topic><topic>SiC</topic><toplevel>online_resources</toplevel><creatorcontrib>Puschkarsky, Katja</creatorcontrib><creatorcontrib>Grasser, Tibor</creatorcontrib><creatorcontrib>Aichinger, Thomas</creatorcontrib><creatorcontrib>Gustin, Wolfgang</creatorcontrib><creatorcontrib>Reisinger, Hans</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore (Online service)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Puschkarsky, Katja</au><au>Grasser, Tibor</au><au>Aichinger, Thomas</au><au>Gustin, Wolfgang</au><au>Reisinger, Hans</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs</atitle><btitle>2018 IEEE International Reliability Physics Symposium (IRPS)</btitle><stitle>IRPS</stitle><date>2018-03</date><risdate>2018</risdate><spage>3B.5-1</spage><epage>3B.5-10</epage><pages>3B.5-1-3B.5-10</pages><eissn>1938-1891</eissn><eisbn>9781538654798</eisbn><eisbn>1538654792</eisbn><abstract>Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔV th after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔV th after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.</abstract><pub>IEEE</pub><doi>10.1109/IRPS.2018.8353560</doi></addata></record>
fulltext fulltext_linktorsrc
identifier EISSN: 1938-1891
ispartof 2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.3B.5-1-3B.5-10
issn 1938-1891
language eng
recordid cdi_ieee_primary_8353560
source IEEE Xplore All Conference Series
subjects BTI
CET
HTGS
Hysteresis
SiC
title Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T04%3A08%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Understanding%20and%20modeling%20transient%20threshold%20voltage%20instabilities%20in%20SiC%20MOSFETs&rft.btitle=2018%20IEEE%20International%20Reliability%20Physics%20Symposium%20(IRPS)&rft.au=Puschkarsky,%20Katja&rft.date=2018-03&rft.spage=3B.5-1&rft.epage=3B.5-10&rft.pages=3B.5-1-3B.5-10&rft.eissn=1938-1891&rft_id=info:doi/10.1109/IRPS.2018.8353560&rft.eisbn=9781538654798&rft.eisbn_list=1538654792&rft_dat=%3Cieee_CHZPO%3E8353560%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c223t-1a2ce09e3f375c37ba5e976957da8c6c1a355b39d4e237fc39823430bc4623523%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=8353560&rfr_iscdi=true