Reliability challenges for 2.5D/3D integration: An overview

Stacking of chips vertically will reduce the interconnection resistance between the chips and also enhance data communication between them. Memory chip to logic chip integration requires close proximity to improve the performance and is an alternate to SOC type chip level integration. Memory to logi...

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Bibliographic Details
Main Authors: Premachandran, C S, Choi, Seungman, Cimino, Salvatore, Tran-Quinn, Thuy, Burrell, Lloyd, Justison, Patrick
Format: Conference Proceeding
Language:English
Subjects:
2.5D
Reliability
TDDB
Online Access:Request full text
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Summary:Stacking of chips vertically will reduce the interconnection resistance between the chips and also enhance data communication between them. Memory chip to logic chip integration requires close proximity to improve the performance and is an alternate to SOC type chip level integration. Memory to logic integration can be done either 2.5D or 3D architecture. Wafer with Through Silicon Via (TSV) is the key enabling technology for this integration. 2.5D is in a nonfunctional wafer while 3D is in a functional wafer. Reliability is a key requirement in accomplishing this complex integration of TSV wafer for both 3D and 2.5D architecture. Wafer level intrinsic reliability for 2.5D and 3D has been studied with respect to BEOL test structures (for EM, TDDB and SM) and to FE OL structures (for TDDB, HCI, BTI and PID). Unique challenges in meeting the reliability of these two complementary technologies are described in this paper.
ISSN:1938-1891
DOI:10.1109/IRPS.2018.8353609