Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array

The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a...

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Main Authors: Kempf, Thibault, Mantelli, Marc, Maugain, Francois, Regnier, Arnaud, Portal, Jean-Michel, Masson, Pascal, Moragues, Jean-Michel, Hesse, Marjorie, della Marca, Vincenzo, Julien, Franck, Niel, Stephan
Format: Conference Proceeding
Language:English
Subjects:
40nm Flash NOR
Annealing
circuit testing
data retention
embedded process
endurance
fixed charge
nitrided oxide
Nitrogen
on-chip characterization
oxide wearout
Presence network agents
Reliability
Stress
Temperature measurement
Threshold voltage
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Summary:The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.
ISSN:2374-8036
DOI:10.1109/IIRW.2017.8361234