Loading…
Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array
The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a...
Saved in:
Main Authors: | , , , , , , , , , , |
---|---|
Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | |
container_end_page | 6 |
container_issue | |
container_start_page | 1 |
container_title | |
container_volume | |
creator | Kempf, Thibault Mantelli, Marc Maugain, Francois Regnier, Arnaud Portal, Jean-Michel Masson, Pascal Moragues, Jean-Michel Hesse, Marjorie della Marca, Vincenzo Julien, Franck Niel, Stephan |
description | The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress. |
doi_str_mv | 10.1109/IIRW.2017.8361234 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_8361234</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8361234</ieee_id><sourcerecordid>8361234</sourcerecordid><originalsourceid>FETCH-LOGICAL-i1334-ab59f6fe623212a754e1141e229f902dd9f7b43ea52c5245c73b562d8da8629a3</originalsourceid><addsrcrecordid>eNotUE1Lw0AUXAXBWvsDxMv-gcTd93aT7FGL1UCl4AcePJSX7ouuJtuS5JJ_b8SehoGZYWaEuNIq1Vq5m7J8fk9B6TwtMNOA5kQsXF5oi0UGiOBOxQwwN0mhMDsXF33_rdSkx2ImPsr2QLtB7mu5fNq8yMO-H2QMQxc8DWEfJcXI1IT4KSfScROoCk0Yxj-HUbGVVsPPneS2Yu_Zy1VD_ZekrqPxUpzV1PS8OOJcvK3uX5ePyXrzUC5v10nQiCahyro6q3nqChoot4a1NpoBXO0UeO_qvDLIZGFnwdhdjpXNwBeepn2OcC6u_3MDM28PXWipG7fHL_AXOvdRFw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array</title><source>IEEE Xplore All Conference Series</source><creator>Kempf, Thibault ; Mantelli, Marc ; Maugain, Francois ; Regnier, Arnaud ; Portal, Jean-Michel ; Masson, Pascal ; Moragues, Jean-Michel ; Hesse, Marjorie ; della Marca, Vincenzo ; Julien, Franck ; Niel, Stephan</creator><creatorcontrib>Kempf, Thibault ; Mantelli, Marc ; Maugain, Francois ; Regnier, Arnaud ; Portal, Jean-Michel ; Masson, Pascal ; Moragues, Jean-Michel ; Hesse, Marjorie ; della Marca, Vincenzo ; Julien, Franck ; Niel, Stephan</creatorcontrib><description>The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.</description><identifier>EISSN: 2374-8036</identifier><identifier>EISBN: 9781538623329</identifier><identifier>EISBN: 1538662329</identifier><identifier>EISBN: 9781538662328</identifier><identifier>EISBN: 1538623323</identifier><identifier>DOI: 10.1109/IIRW.2017.8361234</identifier><language>eng</language><publisher>IEEE</publisher><subject>40nm Flash NOR ; Annealing ; circuit testing ; data retention ; embedded process ; endurance ; fixed charge ; nitrided oxide ; Nitrogen ; on-chip characterization ; oxide wearout ; Presence network agents ; Reliability ; Stress ; Temperature measurement ; Threshold voltage</subject><ispartof>2017 IEEE International Integrated Reliability Workshop (IIRW), 2017, p.1-6</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8361234$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8361234$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kempf, Thibault</creatorcontrib><creatorcontrib>Mantelli, Marc</creatorcontrib><creatorcontrib>Maugain, Francois</creatorcontrib><creatorcontrib>Regnier, Arnaud</creatorcontrib><creatorcontrib>Portal, Jean-Michel</creatorcontrib><creatorcontrib>Masson, Pascal</creatorcontrib><creatorcontrib>Moragues, Jean-Michel</creatorcontrib><creatorcontrib>Hesse, Marjorie</creatorcontrib><creatorcontrib>della Marca, Vincenzo</creatorcontrib><creatorcontrib>Julien, Franck</creatorcontrib><creatorcontrib>Niel, Stephan</creatorcontrib><title>Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array</title><title>2017 IEEE International Integrated Reliability Workshop (IIRW)</title><addtitle>IIRW</addtitle><description>The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.</description><subject>40nm Flash NOR</subject><subject>Annealing</subject><subject>circuit testing</subject><subject>data retention</subject><subject>embedded process</subject><subject>endurance</subject><subject>fixed charge</subject><subject>nitrided oxide</subject><subject>Nitrogen</subject><subject>on-chip characterization</subject><subject>oxide wearout</subject><subject>Presence network agents</subject><subject>Reliability</subject><subject>Stress</subject><subject>Temperature measurement</subject><subject>Threshold voltage</subject><issn>2374-8036</issn><isbn>9781538623329</isbn><isbn>1538662329</isbn><isbn>9781538662328</isbn><isbn>1538623323</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2017</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotUE1Lw0AUXAXBWvsDxMv-gcTd93aT7FGL1UCl4AcePJSX7ouuJtuS5JJ_b8SehoGZYWaEuNIq1Vq5m7J8fk9B6TwtMNOA5kQsXF5oi0UGiOBOxQwwN0mhMDsXF33_rdSkx2ImPsr2QLtB7mu5fNq8yMO-H2QMQxc8DWEfJcXI1IT4KSfScROoCk0Yxj-HUbGVVsPPneS2Yu_Zy1VD_ZekrqPxUpzV1PS8OOJcvK3uX5ePyXrzUC5v10nQiCahyro6q3nqChoot4a1NpoBXO0UeO_qvDLIZGFnwdhdjpXNwBeepn2OcC6u_3MDM28PXWipG7fHL_AXOvdRFw</recordid><startdate>201710</startdate><enddate>201710</enddate><creator>Kempf, Thibault</creator><creator>Mantelli, Marc</creator><creator>Maugain, Francois</creator><creator>Regnier, Arnaud</creator><creator>Portal, Jean-Michel</creator><creator>Masson, Pascal</creator><creator>Moragues, Jean-Michel</creator><creator>Hesse, Marjorie</creator><creator>della Marca, Vincenzo</creator><creator>Julien, Franck</creator><creator>Niel, Stephan</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201710</creationdate><title>Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array</title><author>Kempf, Thibault ; Mantelli, Marc ; Maugain, Francois ; Regnier, Arnaud ; Portal, Jean-Michel ; Masson, Pascal ; Moragues, Jean-Michel ; Hesse, Marjorie ; della Marca, Vincenzo ; Julien, Franck ; Niel, Stephan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1334-ab59f6fe623212a754e1141e229f902dd9f7b43ea52c5245c73b562d8da8629a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2017</creationdate><topic>40nm Flash NOR</topic><topic>Annealing</topic><topic>circuit testing</topic><topic>data retention</topic><topic>embedded process</topic><topic>endurance</topic><topic>fixed charge</topic><topic>nitrided oxide</topic><topic>Nitrogen</topic><topic>on-chip characterization</topic><topic>oxide wearout</topic><topic>Presence network agents</topic><topic>Reliability</topic><topic>Stress</topic><topic>Temperature measurement</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Kempf, Thibault</creatorcontrib><creatorcontrib>Mantelli, Marc</creatorcontrib><creatorcontrib>Maugain, Francois</creatorcontrib><creatorcontrib>Regnier, Arnaud</creatorcontrib><creatorcontrib>Portal, Jean-Michel</creatorcontrib><creatorcontrib>Masson, Pascal</creatorcontrib><creatorcontrib>Moragues, Jean-Michel</creatorcontrib><creatorcontrib>Hesse, Marjorie</creatorcontrib><creatorcontrib>della Marca, Vincenzo</creatorcontrib><creatorcontrib>Julien, Franck</creatorcontrib><creatorcontrib>Niel, Stephan</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kempf, Thibault</au><au>Mantelli, Marc</au><au>Maugain, Francois</au><au>Regnier, Arnaud</au><au>Portal, Jean-Michel</au><au>Masson, Pascal</au><au>Moragues, Jean-Michel</au><au>Hesse, Marjorie</au><au>della Marca, Vincenzo</au><au>Julien, Franck</au><au>Niel, Stephan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array</atitle><btitle>2017 IEEE International Integrated Reliability Workshop (IIRW)</btitle><stitle>IIRW</stitle><date>2017-10</date><risdate>2017</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><eissn>2374-8036</eissn><eisbn>9781538623329</eisbn><eisbn>1538662329</eisbn><eisbn>9781538662328</eisbn><eisbn>1538623323</eisbn><abstract>The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.</abstract><pub>IEEE</pub><doi>10.1109/IIRW.2017.8361234</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | EISSN: 2374-8036 |
ispartof | 2017 IEEE International Integrated Reliability Workshop (IIRW), 2017, p.1-6 |
issn | 2374-8036 |
language | eng |
recordid | cdi_ieee_primary_8361234 |
source | IEEE Xplore All Conference Series |
subjects | 40nm Flash NOR Annealing circuit testing data retention embedded process endurance fixed charge nitrided oxide Nitrogen on-chip characterization oxide wearout Presence network agents Reliability Stress Temperature measurement Threshold voltage |
title | Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T07%3A12%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Impact%20of%20CMOS%20post%20nitridation%20annealing%20on%20reliability%20of%2040nm%20512kB%20embedded%20Flash%20array&rft.btitle=2017%20IEEE%20International%20Integrated%20Reliability%20Workshop%20(IIRW)&rft.au=Kempf,%20Thibault&rft.date=2017-10&rft.spage=1&rft.epage=6&rft.pages=1-6&rft.eissn=2374-8036&rft_id=info:doi/10.1109/IIRW.2017.8361234&rft.eisbn=9781538623329&rft.eisbn_list=1538662329&rft.eisbn_list=9781538662328&rft.eisbn_list=1538623323&rft_dat=%3Cieee_CHZPO%3E8361234%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i1334-ab59f6fe623212a754e1141e229f902dd9f7b43ea52c5245c73b562d8da8629a3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=8361234&rfr_iscdi=true |