Colloidal Synthesized Cobalt Nanoparticles for Nonvolatile Memory Device Application

• Published in: IEEE transactions on semiconductor manufacturing 2018-08, Vol.31 (3), p.356-362
• Main Authors: Yadav, Manoj, Velampati, Ravi Shankar R., Sharma, Rohit
• Format: Article
• Language: English
• Subjects: Aluminum oxide; Atomic layer epitaxy; Capacitance; characterisation; Co-NPs; Coatings; Cobalt; Colloidal synthesis; Colloiding; Data storage; Electric potential; Electrical properties; Fabrication; Memory devices; memory window; Metal oxides; Metals; MOS NVM device; Nanoparticles; Nonvolatile memory; Process control; program/erase; retention; Silicon; Silicon dioxide; Solvents; Spin coating; Synthesis; TEM; Δ<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">Vfb
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2018.2841661

Colloidal synthesized metal nanoparticles (NPs) have great potential to be utilized as economically viable and efficient charge storage floating gate for the non-volatile memory (NVM). Present research work focuses on the NVM device application of colloidal synthesized cobalt (Co) NPs using simple spin coating process. The metal-oxide-semiconductor (MOS) NVM capacitor devices with and without Co-NPs of average size of 5 nm have been fabricated. The MOS NVM and control devices have tunnel oxide (SiO 2 ) thickness of 3.9 nm grown using rapid thermal processing and control dielectric (Al 2 O 3 ) thickness of 10 nm deposited using atomic layer deposition. Colloidal synthesized Cobalt (Co) NPs deposition over silicon dioxide wafer has been done using optimized spin coating process. Electrical characterization of fabricated devices has been done using proxima B1500 semiconductor device parameter analyzer. Capacitance-voltage (C-V) characteristics of fabricated MOS NVM device shows a large flat band voltage shift ( \Delta {V}_{{fb}} ) of around 8.00 V after applying a sweep voltage of −6 V to +6 V and then +6 V to −6 V in C-V response curves. Where, the control device shows negligible \Delta {V}_{fb} in comparison to MOS NVM device. The program and erase characteristics of the fabricated device have also been studied by Fowler-Nordheim tunneling, resulting in 2.31-V memory window for program/erase pulse of ±5 V. The retention capability has been studied by capacitance versus time (C-t) characteristics. This shows a fairly steady C-t response, indicating strong retention capability of fabricated device.