A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a c...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2019-02, Vol.66 (2), p.287-291
Main Authors: Yan, Aibin, Yang, Kang, Huang, Zhengfeng, Zhang, Jiliang, Cui, Jie, Fang, Xiangsheng, Yi, Maoxiang, Wen, Xiaoqing
Format: Article
Language:English
Subjects:
Circuit reliability
double-node upset
Flip-flops
Gating and risering
Integrated circuit reliability
Logic desgin
Low-power electronics
Nodes
radiation hardening
Radiation hardening (electronics)
Recoverability
single node upset
soft error
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Summary:This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2018.2849028