A self-trimming 14b 100MSample/s CMOS DAC

A 14b 100MSample/s CMOS DAC in 0.35 /spl mu/m CMOS achieves high static and dynamic linearity. The static linearity is obtained by a background self-trimming circuit which guarantees 14b INL/DNL. The dynamic linearity is obtained by the use of a track/attenuate stage at the DAC output. Maximum dynam...

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Bibliographic Details
Published in:2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056) 2000, p.44-45
Main Authors: Bugeja, A.R., Bang-Sup Song
Format: Article
Language:English
Subjects:
Calibration
Circuits
Current measurement
Energy consumption
Instruments
Linearity
Rails
Resistors
Switches
Voltage control
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Summary:A 14b 100MSample/s CMOS DAC in 0.35 /spl mu/m CMOS achieves high static and dynamic linearity. The static linearity is obtained by a background self-trimming circuit which guarantees 14b INL/DNL. The dynamic linearity is obtained by the use of a track/attenuate stage at the DAC output. Maximum dynamic linearity is attained up to 100MSample/s update rate, but functionality is retained up to 200MSample/s. Power consumption from 3.3 V is 180 mW at 100MSample/s and 210 mW at 200MSample/s.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2000.839684