A 1 GHz Alpha microprocessor

A 6-way out-of-order issue custom VLSI implementation of the Alpha architecture runs at >1 GHz. The 13.1/spl times/14.7 mm/sup 2/ die contains 15.2 M transistors and utilizes 0.18 /spl mu/m CMOS which includes 7 aluminum interconnect layers and flip-chip packaging. The design of this chip is high...

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Bibliographic Details
Main Authors: Benschneider, B.J., Sungho Park, Allmon, R., Anderson, W., Arneborn, M., Jangho Cho, Changjun Ghoi, Clouser, J., Sangok Han, Hokinson, R., Gyoocheol Hwang, Daesuk Jung, Jaeyoon Kim, Krause, J., Kwack, J., Meier, S., Yongsik Seok, Thierauf, S., Zhou, C.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Diodes
Electronics packaging
Electrostatic discharge
Frequency estimation
Logic
Microprocessors
Routing
Variable structure systems
Voltage
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Summary:A 6-way out-of-order issue custom VLSI implementation of the Alpha architecture runs at >1 GHz. The 13.1/spl times/14.7 mm/sup 2/ die contains 15.2 M transistors and utilizes 0.18 /spl mu/m CMOS which includes 7 aluminum interconnect layers and flip-chip packaging. The design of this chip is highly leveraged from an existing 0.35 /spl mu/m, 6-way issue, 6 metal layer implementation with wire-bond packaging technology. The chip contains two on-chip cache arrays; a 64 kB 2-way set associative instruction cache and 64 kB 2-way set associative dual-ported data cache.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2000.839702