Chip-Package-PCB Co-Design of Power Combiners in SESUB and WLCSP Technology with Re-Distribution Layers

We present SESUB (Semiconductor Embedded in Substrate) and WLCSP (Wafer-Level-Chip-Scale Packaging) integration of Power Combiners for WLAN and 5G applications. The proposed technology solutions offer optimized Electromagnetic-Thermal-Mechanical performances for Energy-Efficient Chip-Package-PCB dis...

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Bibliographic Details
Main Authors: Dinh, Thanh Vinh, Wane, Sidina, Lesenechal, Dominique, Descamps, Philippe, Leyssenne, Laurent, Baion, Damienne
Format: Conference Proceeding
Language:English
Subjects:
BIST
Broadband antennas
Broadband communication
Chip-Package-PCB Co-Design
Inductors
IoT
Loss measurement
Power combiners
Semiconductor device measurement
SESUB
Thermal-EM-Mechanical Co-Analysis
Topology
WLCSP
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Summary:We present SESUB (Semiconductor Embedded in Substrate) and WLCSP (Wafer-Level-Chip-Scale Packaging) integration of Power Combiners for WLAN and 5G applications. The proposed technology solutions offer optimized Electromagnetic-Thermal-Mechanical performances for Energy-Efficient Chip-Package-PCB distributed Co-Design. PDK-Library oriented RLC Lumped-model topologies are compared to broadband distributed Layout design. Prototype demonstrators are designed and experimentally verified for emerging 5G and IoT applications both for frequencies below 6GHz and in the mm-Wave domain (28GHz, 39GHz). Innovative broadband physics-based RLC equivalent circuit models valid from DC to mm-Wave frequencies is proposed and verified against measurement.
ISSN:2375-0995
DOI:10.1109/RFIC.2018.8429033