Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOPLP (fan-out panel-level packaging) method are investigated in this study. Emphasis is placed on the application of a special assembly process called Uni-SIP (Uni-substrate-...

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Main Authors: Ko, Cheng-Ta, Chang, Chieh-Lin, Pan, Jhih-Yuan, Wu, Hsing-Hui, Yong, Qing Xiang, Fan, Nelson, Kuah, Eric, Li, Zhang, Tan, Kim Hwee, Cheung, Y. M., Ng, Eric, Yang, Henry, Kai, Wu, Hao, Ji, Beica, Rozalia, Lin, Marc, Chen, Y.H., Cheng, Zhong, Wee, Koh Sau, Ran, Jiang, Xi, Cao, Lim, Sze Pei, Lau, John, Lee, N.C., Tao, Mian, Lo, Jeffery, Lee, Ricky, Li, Ming, Li, Margie, Lin, Curry, Lin, J.W., Chen, Tony, Xu, Iris
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Compression molding
Electromagnetic compatibility
Fan Out
Heterogeneous Integration
Metals
Panel Level
Plating
RDL
Resists
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Summary:The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOPLP (fan-out panel-level packaging) method are investigated in this study. Emphasis is placed on the application of a special assembly process called Uni-SIP (Uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the thermal cycling test is also performed.
ISSN:2377-5726
DOI:10.1109/ECTC.2018.00061