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Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics

This paper presents a wafer-level pre-packaging technology for power devices. The concept consists in the implementation of a thick 3D patterned copper leadframe ensuring the interconnections of the power devices among them or with the other components of the converter. The metallic leadframe is bon...

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Main Authors: Vladimirova, Kremena, Widiez, Julie, Letowski, Bastien, Perreau, Pierre, Enyedi, Gregory, Coudrain, Perceval, Rouger, Nicolas, Crebier, Jean-Christophe
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Language:English
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creator Vladimirova, Kremena
Widiez, Julie
Letowski, Bastien
Perreau, Pierre
Enyedi, Gregory
Coudrain, Perceval
Rouger, Nicolas
Crebier, Jean-Christophe
description This paper presents a wafer-level pre-packaging technology for power devices. The concept consists in the implementation of a thick 3D patterned copper leadframe ensuring the interconnections of the power devices among them or with the other components of the converter. The metallic leadframe is bonded between two wafers of semiconductor devices enabling the 3D power module integration by the 3D stacking of one or multiple switching cells. Specific technology developments are introduced, practical realizations of the concept are presented and the electrical characterizations of the first prototypes are discussed.
doi_str_mv 10.1109/ECTC.2018.00193
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fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_8429706</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8429706</ieee_id><sourcerecordid>8429706</sourcerecordid><originalsourceid>FETCH-LOGICAL-h250t-b0b9c8890a50caff2cd0fda091c9486cdd55cc990db8e384641cba26ff8c68bf3</originalsourceid><addsrcrecordid>eNotzEFLwzAUAOAoCM65swcv-QOdL0mbJsdRphMKDqx4HOnLS1ftWkmKsn_vQU_f7WPsTsBaCLAP26qp1hKEWQMIqy7YjSiU0bm1Vl2yhVRlmRWl1NdsldIHAEhtcijLBWtep8FTHCglXpPzIboT8U1KfZrJ83cXKGY1fdPA9w4_XdePHW8Ij-M0TN2Zhyny_fRDkW8HwjlOY4_pll0FNyRa_btkb4_bptpl9cvTc7Wps6MsYM5aaC0aY8EVgC4EiR6Cd2AF2txo9L4oEK0F3xpSJte5wNZJHYJBbdqgluz-7-2J6PAV-5OL54PJpS1Bq1_CVVGv</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics</title><source>IEEE Xplore All Conference Series</source><creator>Vladimirova, Kremena ; Widiez, Julie ; Letowski, Bastien ; Perreau, Pierre ; Enyedi, Gregory ; Coudrain, Perceval ; Rouger, Nicolas ; Crebier, Jean-Christophe</creator><creatorcontrib>Vladimirova, Kremena ; Widiez, Julie ; Letowski, Bastien ; Perreau, Pierre ; Enyedi, Gregory ; Coudrain, Perceval ; Rouger, Nicolas ; Crebier, Jean-Christophe</creatorcontrib><description>This paper presents a wafer-level pre-packaging technology for power devices. The concept consists in the implementation of a thick 3D patterned copper leadframe ensuring the interconnections of the power devices among them or with the other components of the converter. The metallic leadframe is bonded between two wafers of semiconductor devices enabling the 3D power module integration by the 3D stacking of one or multiple switching cells. Specific technology developments are introduced, practical realizations of the concept are presented and the electrical characterizations of the first prototypes are discussed.</description><identifier>EISSN: 2377-5726</identifier><identifier>EISBN: 1538649993</identifier><identifier>EISBN: 9781538649992</identifier><identifier>DOI: 10.1109/ECTC.2018.00193</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>3D power module ; Bonding ; Copper ; die-level packaging ; direct copper bonding ; Electrodes ; Lead ; metallic leadframe ; power electronics ; solderless module ; Stacking ; Switches ; Three-dimensional displays ; wafer-level packaging ; wire bondless module</subject><ispartof>2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.1251-1257</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8429706$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,23909,23910,25118,27902,54530,54907</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8429706$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Vladimirova, Kremena</creatorcontrib><creatorcontrib>Widiez, Julie</creatorcontrib><creatorcontrib>Letowski, Bastien</creatorcontrib><creatorcontrib>Perreau, Pierre</creatorcontrib><creatorcontrib>Enyedi, Gregory</creatorcontrib><creatorcontrib>Coudrain, Perceval</creatorcontrib><creatorcontrib>Rouger, Nicolas</creatorcontrib><creatorcontrib>Crebier, Jean-Christophe</creatorcontrib><title>Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics</title><title>2018 IEEE 68th Electronic Components and Technology Conference (ECTC)</title><addtitle>ECTC</addtitle><description>This paper presents a wafer-level pre-packaging technology for power devices. The concept consists in the implementation of a thick 3D patterned copper leadframe ensuring the interconnections of the power devices among them or with the other components of the converter. The metallic leadframe is bonded between two wafers of semiconductor devices enabling the 3D power module integration by the 3D stacking of one or multiple switching cells. Specific technology developments are introduced, practical realizations of the concept are presented and the electrical characterizations of the first prototypes are discussed.</description><subject>3D power module</subject><subject>Bonding</subject><subject>Copper</subject><subject>die-level packaging</subject><subject>direct copper bonding</subject><subject>Electrodes</subject><subject>Lead</subject><subject>metallic leadframe</subject><subject>power electronics</subject><subject>solderless module</subject><subject>Stacking</subject><subject>Switches</subject><subject>Three-dimensional displays</subject><subject>wafer-level packaging</subject><subject>wire bondless module</subject><issn>2377-5726</issn><isbn>1538649993</isbn><isbn>9781538649992</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2018</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotzEFLwzAUAOAoCM65swcv-QOdL0mbJsdRphMKDqx4HOnLS1ftWkmKsn_vQU_f7WPsTsBaCLAP26qp1hKEWQMIqy7YjSiU0bm1Vl2yhVRlmRWl1NdsldIHAEhtcijLBWtep8FTHCglXpPzIboT8U1KfZrJ83cXKGY1fdPA9w4_XdePHW8Ij-M0TN2Zhyny_fRDkW8HwjlOY4_pll0FNyRa_btkb4_bptpl9cvTc7Wps6MsYM5aaC0aY8EVgC4EiR6Cd2AF2txo9L4oEK0F3xpSJte5wNZJHYJBbdqgluz-7-2J6PAV-5OL54PJpS1Bq1_CVVGv</recordid><startdate>20180807</startdate><enddate>20180807</enddate><creator>Vladimirova, Kremena</creator><creator>Widiez, Julie</creator><creator>Letowski, Bastien</creator><creator>Perreau, Pierre</creator><creator>Enyedi, Gregory</creator><creator>Coudrain, Perceval</creator><creator>Rouger, Nicolas</creator><creator>Crebier, Jean-Christophe</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20180807</creationdate><title>Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics</title><author>Vladimirova, Kremena ; Widiez, Julie ; Letowski, Bastien ; Perreau, Pierre ; Enyedi, Gregory ; Coudrain, Perceval ; Rouger, Nicolas ; Crebier, Jean-Christophe</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-h250t-b0b9c8890a50caff2cd0fda091c9486cdd55cc990db8e384641cba26ff8c68bf3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2018</creationdate><topic>3D power module</topic><topic>Bonding</topic><topic>Copper</topic><topic>die-level packaging</topic><topic>direct copper bonding</topic><topic>Electrodes</topic><topic>Lead</topic><topic>metallic leadframe</topic><topic>power electronics</topic><topic>solderless module</topic><topic>Stacking</topic><topic>Switches</topic><topic>Three-dimensional displays</topic><topic>wafer-level packaging</topic><topic>wire bondless module</topic><toplevel>online_resources</toplevel><creatorcontrib>Vladimirova, Kremena</creatorcontrib><creatorcontrib>Widiez, Julie</creatorcontrib><creatorcontrib>Letowski, Bastien</creatorcontrib><creatorcontrib>Perreau, Pierre</creatorcontrib><creatorcontrib>Enyedi, Gregory</creatorcontrib><creatorcontrib>Coudrain, Perceval</creatorcontrib><creatorcontrib>Rouger, Nicolas</creatorcontrib><creatorcontrib>Crebier, Jean-Christophe</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vladimirova, Kremena</au><au>Widiez, Julie</au><au>Letowski, Bastien</au><au>Perreau, Pierre</au><au>Enyedi, Gregory</au><au>Coudrain, Perceval</au><au>Rouger, Nicolas</au><au>Crebier, Jean-Christophe</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics</atitle><btitle>2018 IEEE 68th Electronic Components and Technology Conference (ECTC)</btitle><stitle>ECTC</stitle><date>2018-08-07</date><risdate>2018</risdate><spage>1251</spage><epage>1257</epage><pages>1251-1257</pages><eissn>2377-5726</eissn><eisbn>1538649993</eisbn><eisbn>9781538649992</eisbn><coden>IEEPAD</coden><abstract>This paper presents a wafer-level pre-packaging technology for power devices. The concept consists in the implementation of a thick 3D patterned copper leadframe ensuring the interconnections of the power devices among them or with the other components of the converter. The metallic leadframe is bonded between two wafers of semiconductor devices enabling the 3D power module integration by the 3D stacking of one or multiple switching cells. Specific technology developments are introduced, practical realizations of the concept are presented and the electrical characterizations of the first prototypes are discussed.</abstract><pub>IEEE</pub><doi>10.1109/ECTC.2018.00193</doi><tpages>7</tpages><oa>free_for_read</oa></addata></record>
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subjects 3D power module
Bonding
Copper
die-level packaging
direct copper bonding
Electrodes
Lead
metallic leadframe
power electronics
solderless module
Stacking
Switches
Three-dimensional displays
wafer-level packaging
wire bondless module
title Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T20%3A46%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Solderless%20Leadframe%20Assisted%20Wafer-Level%20Packaging%20Technology%20for%20Power%20Electronics&rft.btitle=2018%20IEEE%2068th%20Electronic%20Components%20and%20Technology%20Conference%20(ECTC)&rft.au=Vladimirova,%20Kremena&rft.date=2018-08-07&rft.spage=1251&rft.epage=1257&rft.pages=1251-1257&rft.eissn=2377-5726&rft.coden=IEEPAD&rft_id=info:doi/10.1109/ECTC.2018.00193&rft.eisbn=1538649993&rft.eisbn_list=9781538649992&rft_dat=%3Cieee_CHZPO%3E8429706%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-h250t-b0b9c8890a50caff2cd0fda091c9486cdd55cc990db8e384641cba26ff8c68bf3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=8429706&rfr_iscdi=true