A high-density, matched hexagonal transistor structure in standard CMOS technology for high-speed applications

In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance caused by the small area. The matching properties of this structure have been investigated, and these results have been compared wit...

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Bibliographic Details
Published in:IEEE transactions on semiconductor manufacturing 2000-05, Vol.13 (2), p.167-172
Main Authors: Van den Bosch, A., Steyaert, M.S.J., Sansen, W.
Format: Article
Language:English
Subjects:
Analog circuits
Circuit synthesis
CMOS
CMOS technology
Drains
Energy consumption
Fabrication
GSM
High speed
Matching
Parasitic capacitance
Semiconductor device modeling
Semiconductor devices
Semiconductors
Testing
Transistors
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Summary:In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance caused by the small area. The matching properties of this structure have been investigated, and these results have been compared with those for traditional finger-style structures. Exploiting the advantages, these transistors are very well suited for high-speed applications with a demand for both good matching and a small area, such as multibit current steering D/A converters or wireless applications. The test chips have been implemented in a standard 0.5-/spl mu/m CMOS technology. No adaptations to the standard technology have been made to realize the structures.
ISSN:0894-6507
1558-2345
DOI:10.1109/66.843632