A Hybrid Design Automation Tool for SAR ADCs in IoT

In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layou...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2018-12, Vol.26 (12), p.2853-2862
Main Authors: Ding, Ming, Harpe, Pieter, Chen, Guibin, Busze, Benjamin, Liu, Yao-Hong, Bachmann, Christian, Philips, Kathleen, van Roermund, Arthur
Format: Article
Language:English
Subjects:
Analog circuits
Analog to digital conversion
Analog to digital converters
Automation
Circuit design
CMOS
Design automation
Digital to analog conversion
Digital to analog converters
Electronic design automation
Energy conversion efficiency
hybrid approach
Hybrid power systems
Internet of Things
Layout
Layouts
low power
Manuals
Mathematical model
Power consumption
Power efficiency
successive approximation register analog-to-digital converter (SAR ADC)
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and 16.7~\mu \text{W} at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2018.2865404