Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs

This work explores, for the first time, wafer level variability of the gate leakage current in advanced FD-SOI MOSFETs. A simple model based on WKB approximation is introduced to model the leakage current and its variance. IL/HK variability segregation is presented using split C-V and gate current d...

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Bibliographic Details
Main Authors: Pradeep, Krishna, Karatsori, T. A., Poiroux, T., Juge, A., Scheer, P., Gouget, G., Josse, E., Ghibando, G.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance-voltage characteristics
compact model
Correlation
Current measurement
direct tunneling
FD-SOI
gate leakage current
global variability
Leakage currents
Logic gates
MOSFET
Semiconductor device modeling
WKB approximation
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Description
Summary:This work explores, for the first time, wafer level variability of the gate leakage current in advanced FD-SOI MOSFETs. A simple model based on WKB approximation is introduced to model the leakage current and its variance. IL/HK variability segregation is presented using split C-V and gate current data without any dedicated test structures.
ISSN:2378-6558
DOI:10.1109/ESSDERC.2018.8486847