An Area and Power Efficient 1-D 4\times 4 Integer DCT Architecture for HEVC

• Main Authors: Bhaskar, Akshay, Jagannadha Naidu, K
• Format: Conference Proceeding
• Language: English
• Subjects: Computer architecture; DCY; Discrete Cosine Transform; Discrete cosine transforms; H.265; HEVC; High Efficiency Video Coding; Integer DCT; Throughput; UHDTV; Video coding
• ISSN: 2325-9418
• DOI: 10.1109/INDICON.2017.8487661

In this paper, we present a one dimensional (1-D) 4\times 4 integer DCT architecture to be used in the High Efficiency Video Coding (HEVC) standard. This architecture serves as a basic building block to construct architectures for different transform lengths like 8\times 8,\ 16\times 16 and 32\times 32 . Also, 2-D integer DCT architectures can be constructed using the proposed architecture and its scaled versions. The architecture detailed in this paper occupies an area of 1572 square microns and consumes 0.65 mW of power at a maximum operating frequency of 200 MHz. Compared to other such architectures, the proposed design achieves a 58.6% savings in area and a 53.9% savings in power. And compared to the reference algorithm, the proposed design saves 66.2% area and 78.5% power. Moreover, the proposed architecture offers higher throughput at a lower operating frequency when compared to other existing architectures. Therefore, with a processing rate of 8 pixels/cycle and a throughput of 1.6 Gsps, the proposed architecture is capable of processing 8K UHD ( 7680\times 4320 ) video at 30 frames per second, which is an application of HEVC.