Enhancing Instruction TLB Resilience to Soft Errors

• Published in: IEEE transactions on computers 2019-02, Vol.68 (2), p.214-224
• Main Authors: Sanchez-Macian, Alfonso, Aranda, Luis Alberto, Reviriego, Pedro, Kiani, Vahdaneh, Maestro, Juan Antonio
• Format: Article
• Language: English
• Subjects: Computer memory; Delays; Error correction; Error correction codes; error detection; Fault tolerance; Fault tolerant systems; Random access memory; reliability; Resilience; Soft errors; Translation lookaside buffer; Virtual memory systems; Virtual private networks
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2018.2874467

A translation lookaside buffer (TLB) is a type of cache used to speed up the virtual to physical memory translation process. Instruction TLBs store virtual page numbers and their related physical page numbers for the last accessed pages of instruction memory. TLBs like other memories suffer soft errors that can corrupt their contents. A false positive due to an error produced in the virtual page number stored in the TLB may lead to a wrong translation and, consequently, the execution of a wrong instruction that can lead to a program hard fault or to data corruption. Parity or error correction codes have been proposed to provide protection for the TLB, but they require additional storage space. This paper presents some schemes to increase the instruction TLB resilience to this type of errors without requiring any extra storage space, by taking advantage of the spatial locality principle that takes place when executing a program.