Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-03, Vol.66 (3), p.967-977
• Main Authors: Jiang, Jianwei, Xu, Yiran, Zhu, Wenyi, Xiao, Jun, Zou, Shichang
• Format: Article
• Language: English
• Subjects: Access time; CMOS; Integrated circuit reliability; Latches; low-voltage SRAM design; Random access memory; reliable terrestrial applications; single event upset (SEU); Single event upsets; Soft error; Soft errors; SRAM bit-cell design; State of the art; Static random access memory; Thermal stability; Threshold voltage; Transistors
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2018.2872507

In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about 2× and 3.4× the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of μ/σ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications.