Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2019-02, Vol.27 (2), p.481-485
• Main Authors: Liu, Jianwei, Chan, Chi-Hang, Sin, Sai-Weng, Seng-Pan, U., Martins, R.P.
• Format: Article
• Language: English
• Subjects: Analog to digital conversion; Analog to digital converters; Bandwidth; Bandwidth mismatches; Calibration; Clocks; CMOS; Delays; Detectors; Estimation; split-digital to analog converter (DAC); successive-approximation-register (SAR) analog-to-digital converter (ADC); time-interleaved (TI); variance based; Very large scale integration; window detector (WD); Windows (intervals)
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2874772

This brief presents a time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an improved variance-based time-skew estimation technique, where we introduce a window detector (WD) based on a SAR ADC. It brings low hardware overhead and 10 4 times faster convergence speed when compared to the prior variance-based time-skew calibration. Postlayout simulation results of a 10-bit, 2-GS/s TI-ADC in 28-nm CMOS process verify the effectiveness of the proposed calibration. The results indicate that the signal noise and distortion ratio/spurious free dynamic range of the ADC improved from 41.9/48.6 to 53.2/63.3 dB after calibration. The total area and power are 0.105 mm 2 and 14.9 mW, respectively, where the WD occupies 0.0015 mm 2 and 0.55 mW.