Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist

Exceptionally low minimum operating voltage (V MIN ) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm 2 high-density bitcell (HDC) and 32Mb array...

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Bibliographic Details
Main Authors: Kim, Daeyeon, Wiedemer, Jami, Kolar, Pramod, Shrivastava, Ayush, Shah, Jinal, Nalam, Satyanand, Baek, Gwanghyeon, Wang, Xiaofei, Guo, Zheng, Karl, Eric
Format: Conference Proceeding
Language:English
Subjects:
Area measurement
Frequency measurement
Power measurement
Random access memory
Silicon carbide
Transistors
Voltage measurement
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Summary:Exceptionally low minimum operating voltage (V MIN ) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm 2 high-density bitcell (HDC) and 32Mb array of 0.107μm 2 high-current bitcell (HCC) achieve the 95 th percentile V MIN of 505mV and 450mV respectively across a temperature range of -10°C to 95°C. A self-induced collapse (SIC) write assist integrated into the 6-T HDC SRAM bitcell array enables 110mV V MIN reduction relative to an unassisted array at the 95 th percentile with negligible power overhead.
ISSN:2158-9682
DOI:10.1109/VLSIT.2018.8510704