Multiple Cell Upset Injection in BRAMs for Xilinx FPGAs

• Published in: IEEE transactions on device and materials reliability 2018-12, Vol.18 (4), p.636-638
• Main Authors: Ullah, Anees, Reviriego, Pedro, Sanchez-Macian, Alfonso, Maestro, Juan Antonio
• Format: Magazinearticle
• Language: English
• Subjects: Clocks; Component reliability; Computer memory; Error correction codes; Fault injection; Fault location; Field programmable gate arrays; MCUs; Radiation effects; Random access memory; Reliability analysis; Resource management; single event effects; Static random access memory; System-on-chip
• ISSN: 1530-4388; 1558-2574
• DOI: 10.1109/TDMR.2018.2878806

On-chip block memories (BRAMs) in SRAM-based FPGAs store critical state information as well as user data which need to be protected against radiation-induced upsets. Therefore, reliability evaluation techniques and upset injection in system components are vital. Previous approaches to fault injection in BRAMs are limited in their abilities to create multiple cell upsets (MCUs) (and, in particular, a kind of MCU called multiple bit upsets) and are vulnerable to unintended state corruption in other memory elements when on-chip injectors are used. This letter proposes an efficient approach for multiple upsets emulation in BRAM contents exploiting the configuration memory cells responsible for initialization. The presented methodology ensures safe fault injection in BRAM contents while preserving the state of other memory elements of the design by using a one-time generated partial bitstream. The approach does not require the time-consuming bitstream generation process for every fault but rather uses run-time single-frame modifications for injection purposes.