On-Die Decoupling Capacitor Optimization for DDR IO Interface Power Rail

In the early stages of DDR memory interface design for SOCs (system on chip), the SOC designer needs to estimate the necessary amount of on-die decoupling capacitance for die floorplanning to meet power rail noise limits. Power rail noise is determined by the DDR interface current profile and the po...

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Bibliographic Details
Main Authors: Wonsae Sim, Sam, Andersson, Warren
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Capacitors
Current Profile
DDR
Impedance
Jitter
On-Die Decap
Optimization
Power Delivery Network
Power Integrity
Power Rail Noise
Rails
Resonant frequency
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Summary:In the early stages of DDR memory interface design for SOCs (system on chip), the SOC designer needs to estimate the necessary amount of on-die decoupling capacitance for die floorplanning to meet power rail noise limits. Power rail noise is determined by the DDR interface current profile and the power delivery network (PDN) impedance, which is dominated by the on-die decoupling in the frequency range of interest. Using an example case of DDR4 at 3200Mb/s, this paper demonstrates an on-die decap optimization method to meet the target power rail noise. In particular, it demonstrates the interaction between the decap value and its associated ESR (effective series resistance) by solution space analysis.
ISSN:2165-4115
DOI:10.1109/EPEPS.2018.8534278