Memory access scheduling

The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the "3-D" structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive refe...

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Bibliographic Details
Main Authors: Rixner, Scott, Dally, William J., Kapasi, Ujval J., Mattson, Peter, Owens, John D.
Format: Conference Proceeding
Language:English
Subjects:
Arithmetic
Bandwidth
Delay
Hardware > Hardware validation
Hardware > Integrated circuits > Semiconductor memory
Laboratories
Out of order
Permission
Pipeline processing
Processor scheduling
Random access memory
Streaming media
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Summary:The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the "3-D" structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive references to different columns within a row and different rows within a bank. This paper introduces memory access scheduling, a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure. Conservative reordering, in which the first ready reference in a sequence is performed, improves bandwidth by 40% for traces from five media benchmarks. Aggressive reordering, in which operations are scheduled to optimize memory bandwidth, improves bandwidth by 93% for the same set of applications. Memory access scheduling is particularly important for media processors where it enables the processor to make the most efficient use of scarce memory bandwidth.
ISSN:1063-6897
2575-713X
DOI:10.1145/339647.339668