Application of a statistical design methodology to low voltage analog MOS integrated circuits

The statistical design of the four-MOSFET structure and the 10-bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in both circuits is provided. Optimization of transistor W and L values, and yield enhancement are demons...

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Bibliographic Details
Main Authors: Tarim, T.B., Ismail, M.
Format: Conference Proceeding
Language:English
Subjects:
Circuit simulation
Design methodology
Fluctuations
Integrated circuit reliability
Integrated circuit yield
Logic
Low voltage
MOS integrated circuits
MOSFETs
Very large scale integration
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Summary:The statistical design of the four-MOSFET structure and the 10-bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in both circuits is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuits are fabricated through the MOSIS 2 /spl mu/m process using MOS transistor Level-3 model parameters. The experimental results are included in the paper.
DOI:10.1109/ISCAS.2000.858702