Low-complexity Check Node Processing for Trellis Min-max Nonbinary LDPC Decoding

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance when the code length is moderate. Check node processing is a bottleneck of the NB-LDPC decoding. In this paper, a novel half-row modified two-extra-column trellis min-max (...

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Bibliographic Details
Main Authors: Thi, Huyen Pham, Tuan, Hung Dao, Trang Dang, Le Dinh, Lee, Hanho, Huu, Tho Nguyen
Format: Conference Proceeding
Language:English
Subjects:
check node processing
Complexity theory
Computer architecture
Decoding
Indexes
layered decoding
Manganese
NB-LDPC
Parity check codes
Throughput
Trellis min-max
VLSI design
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Summary:Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance when the code length is moderate. Check node processing is a bottleneck of the NB-LDPC decoding. In this paper, a novel half-row modified two-extra-column trellis min-max (HR-mTEC-TMM) algorithm is proposed for the check node processing to reduce not only the complexity but also the storage memory. The check node unit (CNU) architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed CNU architecture obtains a reduction of 28.3% for the area and 43.87% for the storage memory with an acceptable error-correcting performance loss, compared to existing work.
ISSN:2162-1039
DOI:10.1109/ATC.2018.8587443