A new strong inversion 5-parameter transistor mismatch model

A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation strong inversion regions, including short channel transistors. The new model is based on splitting the contribution of the mobility degradation par...

Full description

Saved in:
Bibliographic Details
Main Authors: Serrano-Gotarredona, T., Linares-Barranco, B.
Format: Conference Proceeding
Language:English
Subjects:
Degradation
Electronic mail
Intrusion detection
Length measurement
Microelectronics
MOSFETs
Predictive models
Size measurement
Strontium
Testing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 384 vol.4
container_issue
container_start_page 381
container_title
container_volume 4
creator Serrano-Gotarredona, T.
Linares-Barranco, B.
description A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation strong inversion regions, including short channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short channel transistors.
doi_str_mv 10.1109/ISCAS.2000.858768
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_858768</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>858768</ieee_id><sourcerecordid>858768</sourcerecordid><originalsourceid>FETCH-LOGICAL-i87t-70110568916831a89296439932169616169c0e6940c4f75a01e90a5255c54d733</originalsourceid><addsrcrecordid>eNotj81qwzAQhAWl0JL6AdqTXsDuytJKWujFmP4EAj0k9yCcTasS20ESLX37GlJmYA4fDDNC3CtolAJ6XG_7btu0ANB49M76K1GR87BYo_GtuhFVzl8LB4NACm_FUycn_pG5pHn6kHH65pTjPEmszyGFkQsnWVKYcsxlTnKMeQxl-JTjfODTnbg-hlPm6j9XYvfyvOvf6s3767rvNnX0rtQOlnFoPSnrtQqeWrJGE-lWWbJqEQ3AlgwM5ugwgGKCgC3igObgtF6Jh0ttZOb9OcUxpN_95aH-AyizRDI</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A new strong inversion 5-parameter transistor mismatch model</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Serrano-Gotarredona, T. ; Linares-Barranco, B.</creator><creatorcontrib>Serrano-Gotarredona, T. ; Linares-Barranco, B.</creatorcontrib><description>A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation strong inversion regions, including short channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short channel transistors.</description><identifier>ISBN: 9780780354821</identifier><identifier>ISBN: 0780354826</identifier><identifier>DOI: 10.1109/ISCAS.2000.858768</identifier><language>eng</language><publisher>IEEE</publisher><subject>Degradation ; Electronic mail ; Intrusion detection ; Length measurement ; Microelectronics ; MOSFETs ; Predictive models ; Size measurement ; Strontium ; Testing</subject><ispartof>2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000, Vol.4, p.381-384 vol.4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/858768$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/858768$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Serrano-Gotarredona, T.</creatorcontrib><creatorcontrib>Linares-Barranco, B.</creatorcontrib><title>A new strong inversion 5-parameter transistor mismatch model</title><title>2000 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation strong inversion regions, including short channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short channel transistors.</description><subject>Degradation</subject><subject>Electronic mail</subject><subject>Intrusion detection</subject><subject>Length measurement</subject><subject>Microelectronics</subject><subject>MOSFETs</subject><subject>Predictive models</subject><subject>Size measurement</subject><subject>Strontium</subject><subject>Testing</subject><isbn>9780780354821</isbn><isbn>0780354826</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj81qwzAQhAWl0JL6AdqTXsDuytJKWujFmP4EAj0k9yCcTasS20ESLX37GlJmYA4fDDNC3CtolAJ6XG_7btu0ANB49M76K1GR87BYo_GtuhFVzl8LB4NACm_FUycn_pG5pHn6kHH65pTjPEmszyGFkQsnWVKYcsxlTnKMeQxl-JTjfODTnbg-hlPm6j9XYvfyvOvf6s3767rvNnX0rtQOlnFoPSnrtQqeWrJGE-lWWbJqEQ3AlgwM5ugwgGKCgC3igObgtF6Jh0ttZOb9OcUxpN_95aH-AyizRDI</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Serrano-Gotarredona, T.</creator><creator>Linares-Barranco, B.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2000</creationdate><title>A new strong inversion 5-parameter transistor mismatch model</title><author>Serrano-Gotarredona, T. ; Linares-Barranco, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-70110568916831a89296439932169616169c0e6940c4f75a01e90a5255c54d733</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Degradation</topic><topic>Electronic mail</topic><topic>Intrusion detection</topic><topic>Length measurement</topic><topic>Microelectronics</topic><topic>MOSFETs</topic><topic>Predictive models</topic><topic>Size measurement</topic><topic>Strontium</topic><topic>Testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Serrano-Gotarredona, T.</creatorcontrib><creatorcontrib>Linares-Barranco, B.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Serrano-Gotarredona, T.</au><au>Linares-Barranco, B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new strong inversion 5-parameter transistor mismatch model</atitle><btitle>2000 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2000</date><risdate>2000</risdate><volume>4</volume><spage>381</spage><epage>384 vol.4</epage><pages>381-384 vol.4</pages><isbn>9780780354821</isbn><isbn>0780354826</isbn><abstract>A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation strong inversion regions, including short channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short channel transistors.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2000.858768</doi></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 9780780354821
ispartof 2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000, Vol.4, p.381-384 vol.4
issn
language eng
recordid cdi_ieee_primary_858768
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Degradation
Electronic mail
Intrusion detection
Length measurement
Microelectronics
MOSFETs
Predictive models
Size measurement
Strontium
Testing
title A new strong inversion 5-parameter transistor mismatch model
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T18%3A06%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20new%20strong%20inversion%205-parameter%20transistor%20mismatch%20model&rft.btitle=2000%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Serrano-Gotarredona,%20T.&rft.date=2000&rft.volume=4&rft.spage=381&rft.epage=384%20vol.4&rft.pages=381-384%20vol.4&rft.isbn=9780780354821&rft.isbn_list=0780354826&rft_id=info:doi/10.1109/ISCAS.2000.858768&rft_dat=%3Cieee_6IE%3E858768%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i87t-70110568916831a89296439932169616169c0e6940c4f75a01e90a5255c54d733%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=858768&rfr_iscdi=true