Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCube™ Technology

This paper presents a 4T-based SRAM bitcell optimized both for write and read operations at ultra-low voltage (ULV). The proposed bitcell is designed to respond to the requirements of energy constrained systems, as in the case of most IoT-oriented circuits and applications. The use of 3D CoolCube™ t...

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Bibliographic Details
Main Authors: Boumchedda, Reda, Noel, Jean-Philippe, Giraud, Bastien, Makosiej, Adam, Rios, Marco Antonio, Esmanhotto, Eduardo, Bourde-Cice, Emilien, Bellet, Mathis, Turgis, David, Beigne, Edith
Format: Conference Proceeding
Language:English
Subjects:
4T bitcell
Circuit stability
Energy efficiency
Logic gates
Random access memory
Read port
SRAM
Three-dimensional displays
Transistors
ULV
Virtual GND
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Summary:This paper presents a 4T-based SRAM bitcell optimized both for write and read operations at ultra-low voltage (ULV). The proposed bitcell is designed to respond to the requirements of energy constrained systems, as in the case of most IoT-oriented circuits and applications. The use of 3D CoolCube™ technology enables the design of a stable 4T SRAM bitcell by using data-dependent back biasing. The proposed bitcell architecture provides a major reduction of the write operation energy consumption compared to a conventional 6T bitcell. A dedicated read port coupled to a virtual GND (VGND) ensures a full functionality at ULV of read operations. Simulation results show reliable operations down to 0.35 V close to six sigma (6 σ) without any assist techniques (e.g. negative bitlines), achieving in worst case corner 300 ns and 125 ns in write and read access time, respectively. A 6x energy consumption reduction compared to a ULV ultra-low-leakage (ULL) 6T bitcell is demonstrated.
ISSN:2327-8226