Towards Efficient Microarchitecture Design of Simultaneous Localization and Mapping in Augmented Reality Era

Recently, augmented reality technologies are debuting to the mainstream markets. Simultaneous Localization and Mapping (SLAM), which serves as the core to drive augmented reality, enables mobile devices to understand "the reality" by recognizing and understanding the surrounding space. How...

Full description

Saved in:
Bibliographic Details
Main Authors: Chen, Huixiang, Dai, Yuting, Xue, Rui, Zhong, Kan, Li, Tao
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Cameras
CGRA
Feature extraction
Image coding
Memory management
Pipelines
Simultaneous localization and mapping
SLAM
Visualization
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Recently, augmented reality technologies are debuting to the mainstream markets. Simultaneous Localization and Mapping (SLAM), which serves as the core to drive augmented reality, enables mobile devices to understand "the reality" by recognizing and understanding the surrounding space. However, enabling SLAM on mobile devices still faces challenges due to computation and power limitations. Thus, this paper explores the microarchitecture design space of visual SLAM. First, we conduct a characterization to make the image signal processing stage in the front-end image acquisition stage configurable and explore SLAM's sensitivity to individual stages. Our characterization shows that only demosaicing, gamma compression, and denoising in the image signal processing process have significant influences on SLAM's accuracy. Thus, the image signal processor in SoC in traditional mobile devices can be replaced by an approximation logic to save hardware overhead and energy. Second, we propose a new CGRA architecture, called SL-CGRA, specially tailored to SLAM's workload characteristics. It features a two-level memory design, which includes data-redirection layer support for on-chip memory, and an efficient CGRA memory controller stacked through Through-Via Silicon (TSV) for highly efficient off-chip memory access. Besides, PEs in SL-CGRA support different execution modes to exploit the data-level parallelism and task-level parallelism of SLAM. Our evaluation results show that SL-CGRA achieves good performance and energy efficiency.
ISSN:2576-6996
DOI:10.1109/ICCD.2018.00066