Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an initial code optimization to improve the mem...

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Bibliographic Details
Main Authors: Cacciotti, Mattia, Camus, Vincent, Schlachter, Jeremy, Pezzotta, Alessandro, Enz, Christian
Format: Conference Proceeding
Language:English
Subjects:
Field programmable gate arrays
FPGA
Hardware acceleration
hardware-software co-design
Heterogeneous systems
high-level synthesis
image tone mapping
Optimization
Parallel processing
Random access memory
Software
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Summary:In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an initial code optimization to improve the memory access bottleneck, SDSoC pragmas have been introduced to boost system performance through an increased parallelism. Preliminary results have shown significant reductions in the execution time and the energy consumption compared to the conventional software implementation.
ISSN:2164-1706
DOI:10.1109/SOCC.2018.8618490