Implementing 1,024-bit RSA exponentiation on a 32-bit processor core

This paper describes how long-wordlength (1024-bit) modular exponentiation may be implemented on a standard 32-bit microprocessor core with a total execution lime of under 1 second. The design does not use a long-wordlength arithmetic co-processor. Instead all arithmetic operations are reduced to 32...

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Bibliographic Details
Main Authors: Phillips, B.J., Burgess, N.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Arithmetic
Authentication
Cryptography
Energy consumption
Hardware
Microprocessors
Read-write memory
Security
Smart cards
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Summary:This paper describes how long-wordlength (1024-bit) modular exponentiation may be implemented on a standard 32-bit microprocessor core with a total execution lime of under 1 second. The design does not use a long-wordlength arithmetic co-processor. Instead all arithmetic operations are reduced to 32-bit additions, subtractions and binary shifts, and the processor is augmented with a small hardware enhancement to significantly accelerate accumulation of shifted multi-precision numbers. Target performance is achieved by trading fast arithmetic hardware for extra RAM, to facilitate pre-computation of digit multiples and powers. Signed sliding window algorithms are introduced for exponentiation, multiplication and reduction operations, and attention is paid to the integration of enhanced security features such as blinding and verification.
ISSN:2160-0511
2160-052X
DOI:10.1109/ASAP.2000.862384