Fine line panel level plating technology

• Main Authors: Otzlinger, Herbert, Landstorfer, Claudia, Onishi, Tetsuya, Dunkel, Christian, Schroeder, Raoul
• Format: Conference Proceeding
• Language: English
• Subjects: Chemistry; Electrolytes; Packaging; Plating; Substrates; Surface treatment; Wafer scale integration
• ISSN: 2150-5942
• DOI: 10.1109/IMPACT.2018.8625793

New microelectronics applications such as smartphones, automotive computing and server/AI CPUs heavily rely on wafer-level packaging (WLP) to meet performance targets. To meet future cost targets as well, Outsourced Semiconductor Assembly and Test (OSAT) foundries look to panel level packaging (PLP) for significant cost reduction. One of the most difficult parameters for PLP is to establish an economical process for 2/2µm line/space fine line plating with good deposition speed as well as good uniformity. Due to the different handling and panel plating equipment originating from the PCB industry, target line/space dimensions were typically 20/20µm down to 10/10µm, which was easier to achieve considering the lack of rotational movement, large substrate size and substrate surface quality.We present the successful scaling of high speed, extremely uniform plating technology from horizontal wafer plating to vertical panel plating. Using the patented high speed plate technology, we are capable to inject cation-rich electrolyte very close to the substrate surface, with the possibility of disturbing and breaking the surface boundary layer. Within the same plate, we have electrolyte removal holes that allow a direct path to the anode, which allows for uniform electrical fields within 5% all over the substrate surface.