A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing

This paper introduces a voltage-controlled oscillator (VCO)-based nonuniform sampling (NUS) analog-to-digital converter (ADC), which shifts the conventional voltage-domain level crossing to the phase domain, thus eliminating the need for any continuous-time (CT) comparator or reference generator. It...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2019-03, Vol.54 (3), p.623-635
Main Authors: Tzu-Fan Wu, Chen, Mike Shuo-Wei
Format: Article
Language:English
Subjects:
Analog circuits
Analog to digital conversion
Analog to digital converters
Analog-to-digital converter (ADC)
Bandwidth
Calibration
CMOS
Computer architecture
delta–sigma modulator (DSM)
Digital signal processing
Digital signal processors
Digital technology
Dithering
Electric potential
Error analysis
Figure of merit
level crossing
Measurement
Noise
noise shaping
nonuniform sampling (NUS)
oscillator based
Power consumption
pulse-frequency modulation (PFM)
Quantization (signal)
Sampling
Signal processing
Signal resolution
Signal to noise ratio
Voltage controlled oscillators
voltage-controlled oscillator (VCO) based
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Summary:This paper introduces a voltage-controlled oscillator (VCO)-based nonuniform sampling (NUS) analog-to-digital converter (ADC), which shifts the conventional voltage-domain level crossing to the phase domain, thus eliminating the need for any continuous-time (CT) comparator or reference generator. It increases the signal bandwidth and reduces the implementation costs of both analog and digital circuitries compared to the existing voltage-domain NUS ADCs. The signal-to-quantization-noise ratio (SQNR) is improved by the first-order noise shaping and inherent dithering via the free-running oscillation of VCO. The quantization error of the proposed architecture is analyzed, and a phase-domain calibration on the VCO nonlinearity is proposed. Due to the mostly digital architecture and time-based nature of the proposed architecture, the performance and figure of merit (FOM) are expected to improve with the scaled technology. This prototype achieves 200-MHz bandwidth with 60-dB dynamic range (DR) and consumes 19.7 mW of power with an active area of 0.13 mm 2 in 65-nm complementary metal-oxide-semiconductor (CMOS), where the nonuniform digital signal processing (DSP) is performed off chip. The estimated power and area of the nonuniform DSP including the calibration and decimation filter are 30 mW and 0.114 mm 2 , respectively.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2892426