Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect

• Published in: IEEE electron device letters 2019-04, Vol.40 (4), p.566-569
• Main Authors: Seo, Jae Hwa, Yoon, Young Jun, Yu, Eunseon, Sun, Wookyung, Shin, Hyungsoon, Kang, In Man, Lee, Jong-Ho, Cho, Seongjae
• Format: Article
• Language: English
• Subjects: 1T DRAM; Dynamic random access memory; Electron devices; Electron traps; embedded DRAM; Embedded systems; Field effect transistors; Floating bodies; Grain boundaries; grain boundary; Logic gates; MOSFETs; poly-Si; Random access memory; retention; Semiconductor devices; sensing margin; Sensors; Silicon; Transistors
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2019.2901003

A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped {n}^{+} source and drain junctions, nearly intrinsic {n}^{-} channel, 500-nm gate length ( {L}_{{{\mathrm {G}}} ), and 50-nm poly-Si body thickness ( {T}_{{{\mathrm {body}}} ). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of 3.2~{\mu }\text{A}/{\mu }\text{m} and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.