A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency

In this letter, a one-transistor (1T) dynamic random-access memory (DRAM) with SiGe quantum well (QW) is proposed, and its performance is validated through the technology computer-aided design (TCAD) simulation. At the write operation, band-to-band tunneling is used and 1 V or lower programming volt...

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Bibliographic Details
Published in:IEEE electron device letters 2019-04, Vol.40 (4), p.562-565
Main Authors: Yu, Eunseon, Cho, Seongjae, Shin, Hyungsoon, Park, Byung-Gook
Format: Article
Language:English
Subjects:
band-to-band tunneling
CAD
Computer aided design
Computer simulation
Doping
DRAM retention
Dynamic random access memory
low-power operation
One-transistor DRAM
Power demand
Power efficiency
Quantum wells
Random access memory
Sensors
SiGe quantum well
Silicon germanides
Silicon germanium
Transient analysis
Transistors
Tunneling
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Summary:In this letter, a one-transistor (1T) dynamic random-access memory (DRAM) with SiGe quantum well (QW) is proposed, and its performance is validated through the technology computer-aided design (TCAD) simulation. At the write operation, band-to-band tunneling is used and 1 V or lower programming voltage is realized by inserting the SiGe QW beside the drain. This QW also functions as the storage node, which enhances not only the current sensing margin but also the retention time ( \tau _{{\text {ret}}} ) compared with those of all-Si device. At an extremely scaled cell size and sub-10-ns write/erase operations, the proposed device shows 0.2-s-long \tau _{{\text {ret}}} and current ratio > 10 4 . It has been verified that a single cycle of 1T DRAM operations consumes only 93.8 fJ.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2019.2902334