Physical Analysis of Damage Sites Introduced by SEGR in Silicon Vertical Power MOSFETs and Implications for Postirradiation Gate-Stress Test

The damage sites introduced by single-event gate rupture (SEGR) in Si vertical power MOSFETs were physically analyzed to clarify their location and structures. It was found that the damage sites were located on the neck region between p-body diffusions as expected, and the gate oxide was replaced by...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2019-07, Vol.66 (7), p.1710-1714
Main Authors: Kuboyama, Satoshi, Mizuta, Eiichi, Nakada, Yuki, Shindou, Hiroyuki
Format: Article
Language:English
Subjects:
Computer simulation
Electrical properties
Ions
Logic gates
MOSFET
MOSFETs
Neck
Physical analysis
Postgate stress
power MOSFETs
radiation damage
Radiation effects
Silicon
Silicon substrates
single-event gate rupture (SEGR)
Thermal stress
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Summary:The damage sites introduced by single-event gate rupture (SEGR) in Si vertical power MOSFETs were physically analyzed to clarify their location and structures. It was found that the damage sites were located on the neck region between p-body diffusions as expected, and the gate oxide was replaced by Si to electrically connect the gate poly-Si and Si-substrate at the damage sites. As a result, the complicated electrical properties observed on the damaged device were successfully modeled by assuming an Si spike at the damage site in device simulations. It was also suggested that the postgate-stress test with applied voltage higher than that applied during the SEGR test might have forced additional thermal stress on the damage site and have caused the failure attributable to the postgate-stress test itself.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2019.2902871