23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

• Main Authors: Kim, Dongkyun, Park, Minsu, Jang, Sungchun, Song, Jun-Yong, Chi, Hankyu, Choi, Geunho, Choi, Sunmyung, Kim, Jaeil, Kim, Changhyun, Kim, Kyungwhan, Koo, Kibong, Song, Seonghwi, Kim, Yongmi, Lee, Dong Uk, Lee, Jaein, Kim, Daesuk, Kwon, Kihun, Han, Minsik, Choi, Byeongchan, Kim, Hongjung, Ku, Sanghyun, Kim, Yeonuk, Kim, Jongsam, Kim, Sanghui, Seo, Youngsuk, Oh, Seungwook, Im, Dain, Kim, Haksong, Choi, Jonghyuck, Chung, Jinil, Lee, Changhyun, Lee, Yongsung, Cho, Joo-Hwan, Chun, Junhyun, Oh, Jonghoon
• Format: Conference Proceeding
• Language: English
• Subjects: Bit error rate; Clocks; Delays; Pins; SDRAM; Training
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2019.8662320

Required system performance for the computing and server, cost and power forces DRAM to improve its bandwidth, capacity and power. DDR5 SDRAM has been proposed as the next memory solution, with various new functions and circuit techniques to overcome the limitation of DDR4. Speed has been increased to 4.4 - 6.4Gb/s from DDR4's 3.2Gb/s. Energy efficiency has improved by over 30% using a 1.1\mathrm {V}\, V_{\mathrm {DD}} and a 1.8\mathrm {V}\, V_{\mathrm {PP}}. To achieve the performance and power consumption targets DDR5 adopted a small number of command pins with 2cycle decoding, new write training methods, an on-die ECC, an un-matched DQ/DQS scheme, and an equalize scheme for the interface. This paper presents a 16Gb 6.4Gb/s/pin DDR5 SDRAM with a high-speed circuit techniques using a 1.1V DRAM process.