Scalable Modeling of Thermal Impedance in InP DHBTs Targeting Terahertz Applications

In this paper, we report a new scalable model for the thermal impedance of III-V DHBTs that has been developed based on the physics of heat diffusion within the HBT architecture. The heat flows through both the emitter metal layers and toward the substrate are taken into account for the model develo...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2019-05, Vol.66 (5), p.2125-2131
Main Authors: Mukherjee, Chhandak, Couret, Marine, Nodjiadjim, Virginie, Riet, Muriel, Dupuy, J.-Y., Fregonese, Sebastien, Zimmer, Thomas, Maneux, Cristell
Format: Article
Language:English
Subjects:
Compact model
Double heterojunction bipolar transistors
Emitters
Engineering Sciences
Heating systems
III–V HBTs
Impedance
low-frequency S-parameters
Mathematical models
Micro and nanotechnologies
Microelectronics
Parameters
pulse measurement
Scattering parameters
self-heating
Substrates
thermal impedance
Thermal resistance
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Summary:In this paper, we report a new scalable model for the thermal impedance of III-V DHBTs that has been developed based on the physics of heat diffusion within the HBT architecture. The heat flows through both the emitter metal layers and toward the substrate are taken into account for the model development. The model constitutes of individual thermal contributions of the different regions of the intrinsic device and metal layers. On-wafer low-frequency S-parameters measurements have been performed on several device geometries to study the device dynamic self-heating. The model has been validated against the measurements showing good accuracy and scalability. Time-domain pulse measurements have also been performed to correlate with the frequency domain S-parameter measurements.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2019.2906979