Design and Verification of Low Voltage Low Power Dynamic Comparator over PVT Variation

This paper presents a low voltage low power dynamic comparator with 45 process corners verification. In 45 process corner simulation, circuit is simulated with 10% voltage supply variation, five process corners FF, SS, TT, FS, SF variation and temperature variation in between 0°C to 100°C. The compa...

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Bibliographic Details
Main Authors: Rusli, Julie Roslita, Sidek, R.M, Majid, Hasmayadi Abdul, Hassand, W.Z. Wan, Mustafa, Mohd Amrallah, Shafie, Suhaidi
Format: Conference Proceeding
Language:English
Subjects:
ADC
double-tail dynamic comparator
dynamic comparator
low power comparator
SAR ADC
Online Access:Request full text
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Summary:This paper presents a low voltage low power dynamic comparator with 45 process corners verification. In 45 process corner simulation, circuit is simulated with 10% voltage supply variation, five process corners FF, SS, TT, FS, SF variation and temperature variation in between 0°C to 100°C. The comparator is simulated in 0.18µm CMOS technology with supply voltage 0.8 volt using Virtuoso Cadence tool. From simulated result, significant improvement on power consumption and delay is achieved during worst case condition. Details on verification method are presented in this paper.
ISSN:2640-6535
DOI:10.1109/ICSIMA.2018.8688785