A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC

This paper presents a 2x-interleaved 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) that performs 9.73 ENOB under 1-GS/s in 40nm with post-layout simulation. A bootstrapped switch circuit is proposed for 2x-interleaved structure using global master clock without any...

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Bibliographic Details
Main Authors: Hu, Huan-Jui, Cheng, Yi-Shen, Chang, Soon-Jyh
Format: Conference Proceeding
Language:English
Subjects:
Calibration
Clocks
Engines
loop-unrolling
SAR ADC
sub-range strcuture
Switches
Switching circuits
time-interleaved
Timing
timing-skew calibration free
Transistors
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Summary:This paper presents a 2x-interleaved 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) that performs 9.73 ENOB under 1-GS/s in 40nm with post-layout simulation. A bootstrapped switch circuit is proposed for 2x-interleaved structure using global master clock without any timing-skew calibration. In each channel, a sub-range SAR ADC sharing a common coarse SAR ADC with loop-unrolling technique is proposed to enhance speed. This ADC consumes 9.02mW with a figure of merit (FoM) of 10.6fJ/conv-step in post-layout simulation and only covers an area of 0.096mm 2 .
ISSN:2158-1525
DOI:10.1109/ISCAS.2019.8702455