Analysis and Modeling of ASIC Area at Early-Stage Design for Standard Cell Library Selection

Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optima...

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Bibliographic Details
Main Authors: Lim, Yang Wei, Hashim, Shaiful Jahari, Kamsani, Noor Ain, Sidek, Roslina Mohd, Rokhani, Fakhrul Zaman
Format: Conference Proceeding
Language:English
Subjects:
Analysis and Modeling
Area Estimation
ASIC Design
Cell Height
Delays
Frequency synthesizers
Integrated circuit modeling
Libraries
Logic Synthesis
Runtime
Standard Cell
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Description
Summary:Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optimal library for designing area-optimized circuit. The model predicts the area-delay curves for a target circuit based on reduced number of synthesis performed at different frequencies. As compared to the general linear search method, the proposed model with 5 synthesis points results 16.5X-18.6X runtime reduction with average error of 2.74%∼5.74% in different height libraries implementation. This shows that the proposed model is beneficial for area optimal library selection at the early stage of design.
ISSN:2158-1525
DOI:10.1109/ISCAS.2019.8702691