Better Late Than Never : Verification of Embedded Systems After Deployment

This paper investigates the benefits of verifying embedded systems after deployment. We argue that one reason for the huge state spaces of contemporary embedded and cyber-physical systems is the large variety of operating contexts, which are unknown during design. Once the system is deployed, these...

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Bibliographic Details
Main Authors: Ring, Martin, Bornebusch, Fritjof, Luth, Christoph, Wille, Robert, Drechsler, Rolf
Format: Conference Proceeding
Language:English
Subjects:
Delays
Embedded systems
Hardware
Switches
Unified modeling language
Online Access:Request full text
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Summary:This paper investigates the benefits of verifying embedded systems after deployment. We argue that one reason for the huge state spaces of contemporary embedded and cyber-physical systems is the large variety of operating contexts, which are unknown during design. Once the system is deployed, these contexts become observable, confining several variables. By this, the search space is dramatically reduced, making verification possible even on the limited resources of a deployed system. In this paper, we propose a design and verification flow which exploits this observation. We show how specifications are transferred to the deployed system and verified there. Evaluations on a number of case studies demonstrate the reduction of the search space, and we sketch how the proposed approach can be employed in practice.
ISSN:1558-1101
DOI:10.23919/DATE.2019.8714967