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SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET
This paper proposes soft error immune flip-flop (SEIFF) for mitigating single event upset (SEU) in flip-flops (FFs) and impact of single event transient (SET) in combinational-logic. SEIFF mitigates the SET without enlarging setup-time and delay; there is no overhead in circuit performance. Alpha an...
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Main Authors: | , , , , , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
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Summary: | This paper proposes soft error immune flip-flop (SEIFF) for mitigating single event upset (SEU) in flip-flops (FFs) and impact of single event transient (SET) in combinational-logic. SEIFF mitigates the SET without enlarging setup-time and delay; there is no overhead in circuit performance. Alpha and proton tests validate the mitigation efficiency in SEIFF manufactured on 10 nm FinFET technology. |
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ISSN: | 1938-1891 |
DOI: | 10.1109/IRPS.2019.8720513 |