Implementation of a CMOS Operational Amplifier using Composite Cascode Stages

• Main Authors: Sai Kumar, K., Lokesh Krishna, K., Sidda Reddy, P. R., Mohan Sai, D., Naga Sai Rishwanth, C., Venu Prasad, B.
• Format: Conference Proceeding
• Language: English
• Subjects: Bandwidth; Communication systems; DC gain; Impedance; low power; Operational amplifiers; Power supplies; Rails; size and bandwidth; slew rate; Transistors; W/L ratio
• ISSN: 2575-7288
• DOI: 10.1109/ICACCS.2019.8728335

In this paper the design and implementation of a cascode amplifier stage based CMOS operational amplifier is presented. Cascode based operational amplifiers (op-amp) has the property that it is capable of handling input common mode (CM) signal levels close to operating supply voltages (V DD ). Every transistor size in the op-amp is designed, validated and operated at V DD =1.5V. Incorporating higher bandwidth enables the amplifier circuit to operate for high speed applications and high gain supports the circuit to operate efficiently in a closed loop feedback system with reasonable stability. The main parameters considered are DC gain, slew rate, power dissipation, phase margin, unity gain bandwidth and CMRR. The proposed cascode amplifier stage is simulated using Cadence Virtuoso schematic editor, whereas the layout has been designed using Virtuoso. The designed op-amp using cascode stage amplifiers provide a DC voltage gain of 68.6dB and a UGB (unity gain bandwidth) of 420MHz at 0.2pF. The power dissipation is calculated to be 114µW, slew rate is 72.8V/µs, CMRR is approximately 102.6dB and occupied area is 0.032mm 2 .